Examples of semiconductor devices include field effect transistors (FETs), light emitting diodes (LEDs), and the like. For LEDs, for example, Group III-V semiconductors made of compounds of Group III and Group V elements are used.
A Group III nitride semiconductor using Al, Ga, In, or the like as a Group III element and using N as a Group V element has a high melting point and a high dissociation pressure of nitrogen, which makes it difficult to perform bulk single crystal growth. Further, conductive single crystal substrates having large diameter are not available at low cost. Therefore, such a semiconductor is typically formed on a sapphire substrate.
However, since the sapphire substrate has insulating property, electric current does not flow in the substrate. Accordingly, a light emitting diode having a lateral structure in which electric current flows in a lateral direction has conventionally been used. This structure is obtained by partially removing a semiconductor laminate formed by sequentially growing an n-type Group III nitride semiconductor layer, an active layer (light emitting layer), and a p-type Group III nitride semiconductor layer on a sapphire substrate, to expose the n-type Group III nitride semiconductor layer, and providing an n-type electrode and a p-type electrode on the exposed n-type Group III nitride semiconductor layer and the p-type Group III nitride semiconductor layer, respectively.
On the other hand, in recent years, the following techniques for obtaining LED chips have been studied. After forming a buffer layer made of a certain element other than a Group III element (for example, Al, Ga, or the like) on a sapphire substrate, a semiconductor laminate including a light-emitting layer is formed. The semiconductor laminate is supported by a conductive support body, and then a sapphire substrate is separated (lifted off) by selectively dissolving the buffer layer by chemical etching. The conductive support body and the semiconductor laminate are sandwiched between a pair of electrodes. Note that a “buffer layer” herein is a buffer layer for epitaxial growth of a semiconductor laminate, which also serves as a lift-off layer for separating the semiconductor laminate from a sapphire substrate.
Examples of processes for manufacturing a III nitride semiconductor LED chip having such a structure include a typical chemical lift-off process in which a lift-off layer made of a metal other than Group III elements or a nitride of such metal is etched to separate an epitaxial layer from a sapphire substrate, or a photochemical lift-off process in which etching is performed while activating a lift-off layer by irradiation with light such as ultraviolet light. They are processes in which a lift-off layer is immersed in a certain solution thereby dissolving the lift-off layer to lift off an epitaxial layer from a growth substrate, and such processes are collectively referred to as “chemical lift-off processes” in this specification. An alternative expression may be “a growth substrate is lifted off from an epitaxial layer”.
Here, a method of manufacturing vertically structured Group III nitride semiconductor LED chips that is described in PTL 1 (WO 2011/055462) will be explained with reference to FIGS. 6(A) to 6(F) and FIGS. 7(A) and 7(B). FIGS. 6(A) to 6(F) are schematic cross-sectional views illustrating the steps of a method of manufacturing conventional vertically structured Group III nitride semiconductor LED chips 500. First, a semiconductor laminate 503 is formed on a growth substrate 501 with a lift-off layer 502 therebetween by sequentially stacking a first conductivity type Group III nitride semiconductor layer 504, a light emitting layer 505, and a second conductivity type Group III nitride semiconductor layer 506, the second conductivity type being different from the first conductivity type (FIG. 6(A)). Next, the semiconductor laminate 503 and the lift-off layer 502 are partially removed to partially expose the growth substrate 501, thereby forming a plurality of separate semiconductor structures 507 are formed by partially removing the semiconductor laminate 503 (FIG. 6(B)). Subsequently, a conductive support body 512 is formed, which integrally supports the plurality of semiconductor structures 507 and also serves as a lower electrode (FIG. 6(C)). Further, the lift-off layer 502 is removed using a chemical lift-off process, thereby separating the growth substrate 501 from the plurality of semiconductor structures 507 (FIG. 6(D)). After that, upper electrodes 516 are formed on the separation side of the semiconductor structures 507 (FIG. 6(E)); finally, the conductive support body 512 is divided by cutting or the like along the broken lines shown in FIG. 7(A) between the semiconductor structures 507, thus singulating a plurality of LED chips 500 having the respective semiconductor structures 507 supported by the divided conductive support bodies 512A (FIG. 6(F)).
FIG. 7(A) is a schematic top view of a wafer in a state of FIG. 6(E) where the plurality of semiconductor structures which have not been singulated are formed. FIG. 6(E) is a cross-sectional view taken along a broken line in FIG. 7(A). FIG. 7(B) is a schematic side view of one of the LED chips 500 singulated along the broken lines in FIG. 7(A). Thus, in PTL 1, through-grooves 514 are provided along cut lines of the singulation (broken lines) in portions of the conductive support body 512 located between adjacent semiconductor structures 507. Accordingly, when the lift-off layer 502 is removed as in FIGS. 6(C) to 6(D), an etchant is supplied via the through-grooves 514 to surround the semiconductor structures 507. Further, the lift-off layer 502 right under the semiconductor structures 507 is etched from the outer peripheral portion of the semiconductor structures to the center portion thereof.
Here, in PTL 1, as shown in FIG. 7(A), the transverse cross section of the semiconductor structures 507 has a circular shape or a 4 n-gon shape (“n” is a positive integer) having rounded corners. If the transverse cross section of the semiconductor structures has a 4 n-gon shape without rounded corners, X-shaped cracks extending from the vicinity of the corners to the center portion would be formed in the individual semiconductor structures at a considerable rate after the lift-off as shown in FIG. 8(A). In PTL 1, the shape of the semiconductor structures is as described above, so that stresses can be prevented from being concentrated at the corners (the vectors of the etching proceeding from the periphery of the light emitting structures meet) during etching; thus, the formation of the above X-shape cracks can be prevented.